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FEATURES All Grades 14-Bit Monotonic Over the Full Temperature Range Low Cost 14-Bit Upgrade for 12-Bit Systems 14-Bit Parallel Load with Double Buffered Inputs Small 24-Pin, 0.3 DIP and SOIC Low Output Leakage (<20 nA) Over the Full Temperature Range APPLICATIONS Microprocessor Based Control Systems Digital Audio Precision Servo Control Control and Measurement in High Temperature Environments
LC2MOS P-Compatible 14-Bit DAC AD7538
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7538 is a 14-bit monolithic CMOS D/A converter which uses laser trimmed thin-film resistors to achieve excellent linearity. The DAC is loaded by a single 14-bit wide word using standard Chip Select and Memory Write Logic. Double buffering, which is optional using LDAC, allows simultaneous update in a system containing multiple AD7538s. A novel low leakage configuration (U.S. Patent No. 4,590,456) enables the AD7538 to exhibit excellent output leakage current characteristics over the specified temperature range. The AD7538 is manufactured using the Linear Compatible CMOS (LC2MOS) process. It is speed compatible with most microprocessors and accepts TTL or CMOS logic level inputs.
1. Guaranteed Monotonicity The AD7538 is guaranteed monotonic to 14-bits over the full temperature range for all grades. 2. Low Cost The AD7538, with its 14-bit dynamic range, affords a low cost solution for 12-bit system upgrades. 3. Small Package Size The AD7538 is packaged in a small 24-pin, 0.3" DIP and a 24-pin SOIC. 4. Low Output Leakage By tying VSS (Pin 24) to a negative voltage, it is possible to achieve a low output leakage current at high temperatures. 5. Wide Power Supply Tolerance The device operates on a +12 V to +15 V VDD, with a 5% tolerance on this nominal figure. All specifications are guaranteed over this range.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD7538-SPECIFICATIONS1 (V V
Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Full-Scale Error +25C TMIN to TMAX Gain Temperature Coefficient3; Gain/Temperature Output Leakage Current IOUT (Pin 3) +25C TMIN to TMAX TMIN to TMAX REFERENCE INPUT Input Resistance, Pin 1 J, K Versions 14 2 1 4 8 2 5 10 25 3.5 10 14 1 1 4 5 2 5 10 25 3.5 10
= +11.4 V to +15.75 V2, VREF = +10 V; VPIN3 = VPIN4 = 0 V, SS = -300 mV. All specifications TMIN to TMAX unless otherwise noted.)
DD
A, B Versions
S Version
T Version
Units
Test Conditions/Comments
14 2 1 4 10 2 5 20 150 3.5 10
14 1 1 4 6 2 5 20 150 3.5 10
Bits LSB max LSB max LSB max LSB max ppm/C typ nA max nA max nA max
All Grades Guaranteed Monotonic Over Temperature. Measured Using Internal RFB DAC Registers Loaded with All 1s.
All Digital Inputs 0 V VSS = -300 mV VSS = 0 V Typical Input Resistance = 6 k
k min k max
DIGITAL INPUTS VIH (Input High Voltage) VIL (Input Low Voltage) IIN (Input Current) +25C TMIN to TMAX CIN (Input Capacitance)3 POWER SUPPLY VDD Range VSS Range IDD
2.4 0.8 1 10 7
2.4 0.8 1 10 7
2.4 0.8 1 10 7
2.4 0.8 1 10 7
V min V max A max A max pF max VIN = 0 V or VDD
11.4/15.75 -200/-500 4 500
11.4/15.75 -200/-500 4 500
11.4/15.75 -200/-500 4 500
11.4/15.75 -200/-500 4 500
V min/V max mV min/mV max mA max A max
Specification Guaranteed Over This Range All Digital Inputs VIL or VIH All Digital Inputs 0 V or VDD
AC PERFORMANCE CHARACTERISTICS
Parameter Output Current Settling Time 1.5
These characteristics are included for Design Guidance only and are not subject to test. (VDD = +11.4 V to +15.75 V, VREF = +10 V, VPIN3 = VPIN4 = O V, VSS = O V or -300 mV, Output Amplifier is AD711 except where noted.)
Units s max Test Conditions/Comments To 0.003% of Full-Scale Range. IOUT Load= 100 , CEXT = 13 pF. DAC Register Alternately Loaded with All 1s and All 0s. Typical Value of Settling Time Is 0.8 s. Measured with VREF = 0 V. IOUT Load = 100 , CEXT = 13 pF. DAC Register Alternately Loaded with All 1s and All 0s. VREF = 10 V, 10 kHz Sine Wave DAC Register Loaded with All 0s. VDD = 5% DAC Register Loaded with All 1s DAC Register Loaded with All 0s Measured Between RFB and IOUT
TA = +25 C TA = TMIN, TMAX
Digital to Analog Glitch Impulse
20
nV-sec typ
Multiplying Feedthrough Error Power Supply Rejection Gain/VDD Output Capacitance COUT (Pin 3) COUT (Pin 3) Output Noise Voltage Density (10 Hz-100 kHz)
3 0.01 260 130 15
5 0.02 260 130
mV p-p typ
% per % max pF max pF max nVHz typ
NOTES Temperature range as follows: J, K Versions: 0C to +70C A, B Versions: -25C to +85C S, T Versions: -55C to +125C 2 Specifications are guaranteed for a V DD of +11.4 V to +15.75 V. At V DD = 5 V, the device is fully functional with degraded specifications. 3 Sample tested to ensure compliance. Specifications subject to change without notice.
-2-
REV. A
AD7538 TIMING CHARACTERISTICS1 All specifications T
Parameter t1 t2 t3 t4 t5 t6 Limit at TA = +25 C 0 0 170 170 140 20 Limit at TA = 0 C to +70 C TA = -25 C to +85 C 0 0 200 200 160 20
(VDD = +11.4 V to +15.75 V, VREF = +10 V, VPIN3 = VPIN4 = 0 V, VSS = 0 V or -300 mV. MIN to TMAX unless otherwise noted. See Figure 1 for Timing Diagram.)
Limit at TA = -55 C to +125 C 0 0 240 240 180 30
Units ns min ns min ns min ns min ns min ns min
Test Conditions/Comments CS to WR Setup Time CS to WR Hold Time LDAC Pulse Width Write Pulse Width Data Setup Time Data Hold Time
NOTES 1 Temperature range as follows: J, K Versions: 0C to +70C A, B Versions: -25C to +85C S, T Versions: -55C to +125C Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(TA= +25C unless otherwise stated)
VDD (Pin 23) to DGND . . . . . . . . . . . . . . . . . . . -0.3 V, +17 V VSS (Pin 24) to AGND . . . . . . . . . . . . . . . . . . . -15 V, +0.3 V VREF (Pin 1) to AGND . . . . . . . . . . . . . . . . . . . . . . . . . 25 V VRFB (Pin 2) to AGND . . . . . . . . . . . . . . . . . . . . . . . . . 25 V Digital Input Voltage (Pins 6-22) to DGND . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, VDD +0.3 V VPIN3 to DGND . . . . . . . . . . . . . . . . . . . . -0.3 V, VDD +0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . -0.3 V, VDD +0.3 V Power Dissipation (Any Package) To +75C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW Derates Above +75C . . . . . . . . . . . . . . . . . . . . 10 mW/C
Operating Temperature Range Commercial (J, K Versions) . . . . . . . . . . . . . . 0C to +70C Industrial (A, B Versions) . . . . . . . . . . . . . . -25C to +85C Extended (S, T Versions) . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300C
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7538 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATION DIP, SOIC
Figure 1. Timing Diagram
REV. A
-3-
AD7538
TERMINOLOGY
RELATIVE ACCURACY
in Least Significant Bits. Gain error is adjustable to zero with an external potentiometer.
DIGITAL-TO-ANALOG GLITCH IMPULSE
Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error and is normally expressed in Least Significant Bits or as a percentage of full-scale reading.
DIFFERENTIAL NONLINEARITY
The amount of charge injected from the digital inputs to the analog output when the inputs change state is called Digitalto-Analog Glitch Impulse. This is normally specified as the area of the glitch in either pA-secs or nV-secs depending upon whether the glitch is measured as a current or voltage. It is measured with VREF = AGND.
OUTPUT CAPACITANCE
Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB max over the operating temperature range ensures monotonicity.
GAIN ERROR
This is the capacitance from IOUT to AGND.
OUTPUT LEAKAGE CURRENT
Gain error is a measure of the output error between an ideal DAC and the actual device output. It is measured with all 1s in the DAC after offset error has been adjusted out and is expressed
Output Leakage Current is current which appears at IOUT with the DAC register loaded to all 0s.
MULTIPLYING FEEDTHROUGH ERROR
This is the ac error due to capacitive feedthrough from VREF terminal to IOUT with DAC register loaded to all zeros.
ORDERING GUIDE
Model AD7538JN AD7538KN AD7538JR AD7538KR AD7538AQ AD7538BQ AD7538SQ AD7538TQ
Temperature Range 0C to +70C 0C to +70C 0C to +70C 0C to +70C -25C to +85C -25C to +85C -55C to +125C -55C to +125C
Relative Accuracy 2 LSB 1 LSB 2 LSB 1 LSB 2 LSB 1 LSB 2 LSB 1 LSB
Full-Scale Error 8 LSB 4 LSB 8 LSB 4 LSB 8 LSB 4 LSB 8 LSB 4 LSB
Package Option* N-24 N-24 R-24 R-24 Q-24 Q-24 Q-24 Q-24
*N = Plastic DIP; Q = Cerdip; R = SOIC.
PIN FUNCTION DESCRIPTION
Pin 11 12 13 14 15 6-19 20 21 22
Mnemonic VREF RFB IOUT AGND DGND DB13-DB0 LDAC CS WR
Description Voltage Reference. Feedback Resistor. Used to close the loop around an external op amp. Current Output Terminal. Analog Ground Digital Ground Data Inputs. Bit 13 (MSB) to Bit 0 (LSB). Chip Select Input. Active LOW. Asynchronous Load DAC Input. Active LOW. Write Input. Active LOW. CS 0 1 0 1 X LDAC 1 0 0 1 1 WR 0 X 0 X 1 OPERATION Load Input Register. Load DAC Register from Input Register. Input and DAC Registers are Transparent. No Operation. No Operation.
NOTE: X Don't Care.
23 24
VDD VSS
+12 V to +15 V supply input. Bias pin for High Temperature Low Leakage configuration. To implement low leakage system, the pin should be at a negative voltage. See Figures 4 and 5 for recommended circuitry. -4- REV. A
AD7538
D/A SECTION
Figure 2 shows a simplified circuit diagram for the AD7538 D/A section. The three MSBs of the 14-bit Data Word are decoded to drive the seven switches A-G. The 11 LSBs of the Data Word consist of an R-2R ladder operated in a current steering configuration.
The R-2R ladder current is 1/8 of the total reference input current. 7/8 I flows in the parallel ladder structure. Switches A-G steer equally weighted currents between IOUT and AGND. Since the input resistance at VREF is constant, it may be driven by a voltage source or a current source of positive or negative polarity.
CIRCUIT INFORMATION
Figure 2. Simplified Circuit Diagram for the AD7538 D/A Section
EQUIVALENT CIRCUIT ANALYSIS
Figure 3 shows an equivalent circuit for the analog section of the AD7538 D/A converter. The current source ILEAKAGE is composed of surface and junction leakages. The resistor RO denotes the equivalent output resistance of the DAC which varies with input code. COUT is the capacitance due to the current steering switches and varies from about 90 pF to 180 pF (typical values) depending upon the digital input. g(VREF, N) is the Thevenin equivalent voltage generator due to the reference input voltage, VREF, and the transfer function of the DAC ladder, N.
Figure 4. Unipolar Binary Operation
Table I. Unipolar Binary Code Table for AD7538
Figure 3. AD7538 Equivalent Analog Output Circuit
DIGITAL SECTION
The digital inputs are designed to be both TTL and 5 V CMOS compatible. All logic inputs are static protected MOS gates with typical input currents of less than 1 nA. To minimize power supply currents, it is recommended that the digital input voltages be driven as close as possible to 0 V and 5 V logic levels.
UNIPOLAR BINARY OPERATION (2-QUADRANT MULTIPLICATION)
Binary Number In DAC Register MSB LSB 11 1111 1111 1111
Analog Output, VOUT
16383 -V IN 16384 8192 -VIN = -1/ 2V IN 16384
1 -VIN 16384
10 0000 0000 0000
Figure 4 shows the circuit diagram for unipolar binary operation. With an ac input, the circuit performs 2 quadrant multiplication. The code table for Figure 4 is given in Table I. Capacitor C1 provides phase compensation and helps prevent overshoot and ringing when high-speed op amps are used.
00 0000 0000 0001 00 0000 0000 0000
0V
REV. A
-5-
AD7538
For zero offset adjustment, the DAC register is loaded with all 0s and amplifier offset (VOS) adjusted so that VOUT is 0 V. Adjusting VOUT to 0 V is not necessary in many applications, but it is recommended that VOS be no greater than (25 x 10-6) (VREF) to maintain specified DAC accuracy (see Applications Hints). Full-scale trimming is accomplished by loading the DAC register with all 1s and adjusting R1 so that VOUTA = -VIN (16383/16384). For high temperature operation, resistors and potentiometers should have a low Temperature Coefficient. In many applications, because of the excellent Gain T.C. and Gain Error specifications of the AD7538, Gain Error trimming is not necessary. In fixed reference applications, full scale can also be adjusted by omitting R1 and R2 and trimming the reference voltage magnitude.
BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION) Table II. Bipolar Code Table for Offset Binary Circuit of Figure 5.
Binary Number In DAC Register MSB LSB
Analog Output VOUT
11 1111 1111 1111
8191 +V IN 8192 1 +VIN 8192
0V
10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 00 0000 0000 0000
The recommended circuit diagram for bipolar operation is shown in Figure 5. Offset binary coding is used. The code table for Figure 5 is given in Table II. With the DAC loaded to 10 0000 0000 0000, adjust R1 for VO = 0 V. Alternatively, one can omit R1 and R2 and adjust the ratio of R5 and R6 for VO = 0 V. Full-scale trimming can be accomplished by adjusting the amplitude of VIN or by varying the value of R7. The values given for R1, R2 are the minimum necessary to calibrate the system for resistors, R5, R6, R7 ratio matched to 0.1%. System linearity error is independent of resistor ratio matching and is affected by DAC linearity error only. When operating over a wide temperature range, it is important that the resistors be of the same type so that their temperature coefficients match. For further information sec "CMOS DAC Application Guide", 3rd Edition, Publication Number G872b-8-1/89 available from Analog Devices.
1 -VIN 8192
8191 -V IN 8192
VSS should be tied to a voltage of approximately -0.3 V as in Figures 4 and 5. A simple resistor divider (R3, R4) produces approximately -300 mV from -15 V. The capacitor C2 in parallel with R3 is an integral part of the low leakage configuration and must be 4.7 F or greater. Figure 6 is a plot of leakage current versus temperature for both conditions. It clearly shows the improvement gained by using the low leakage configuration.
Figure 6. Graph of Typical Leakage Current vs. Temperature for AD7538
PROGRAMMABLE GAIN AMPLIFIER
The circuit shown in Figure 7 provides a programmable gain amplifier (PGA). In it the DAC behaves as a programmable resistance and thus allows the circuit gain to be digitally controlled.
Figure 5. Bipolar Operation
LOW LEAKAGE CONFIGURATION
For CMOS Multiplying D/A converters, as the device is operated at higher temperatures, the output leakage current increases. For a 14-bit resolution system, this can be a significant source of error. The AD7538 features a leakage reduction configuration (U.S. Patent No. 4,590,456) to keep the leakage current low over an extended temperature range. One may operate the device with or without this configuration. If VSS (Pin 24) is tied to AGND then the DAC will exhibit normal output leakage current at high temperatures. To use the low leakage facility, -6-
Figure 7. Programmable Gain Amplifier (PGA)
REV. A
AD7538
The transfer function of Figure 7 is:
MICROPROCESSOR INTERFACING
R V Gain = OUT = - EQ V IN RFB
(1)
REQ is the equivalent transfer impedance of the DAC from the VREF pin to the IOUT pin and can be expressed as REQ = 2n RIN N (2)
The AD7538 is designed for easy interfacing to 16-bit microprocessors and can be treated as a memory mapped peripheral. This reduces the amount of external logic needed for interfacing to a minimal.
AD7538-8086 INTERFACE
Where: n is the resolution of the DAC Where: N is the DAC input code in decimal Where: RIN is the constant input impedance Where: of the DAC (RIN = RLAD) Substituting this expression into Equation 1 and assuming zero gain error for the DAC (RIN = RFB) the transfer function simplifies to
VOUT 2n =- V IN N
Figure 8 shows the 8086 processor interface to a single device. In this setup the double buffering feature (using LDAC) of the DAC is not used. The 14-bit word is written to the DAC in one MOV instruction and the analog output responds immediately.
(3)
Figure 8. AD7538-8086 Interface Circuit
The ratio N/2n is commonly represented by the term D and, as such, is the fractional representation of the digital input word.
VOUT -2n -1 =- = V IN N D
(4)
Equation 4 indicates that the gain of the circuit can be varied from 16,384 down to unity (actually 16,384/16,383) in 16,383 steps. The all 0s code is never applied. This avoids an openloop condition thereby saturating the amplifier. With the all 0s code excluded there remains 2n - 1 possible input codes allowing a choice of 2n - 1 output levels. In dB terms the dynamic range is
In a multiple DAC system the double buffering of the AD7538 allows the user to simultaneously update all DACs. In Figure 9, a 14-bit word is loaded to the Input Registers of each of the DACs in sequence. Then, with one instruction to the appropriate address, CS4 (i.e., LDAC) is brought low, updating all the DACs simultaneously.
20 log 10
VOUT = 20 log 10 (2n -1) = 84 dB. V IN
APPLICATION HINTS
Output Offset: CMOS D/A converters in circuits such as Figures 4 and 5 exhibit a code dependent output resistance which in turn can cause a code dependent error voltage at the output of the amplifier. The maximum amplitude of this error, which adds to the D/A converter nonlinearity, depends on VOS, where VOS is the amplifier input offset voltage. To maintain specified accuracy with VREF at 10 V, it is recommended that VOS be no greater than 0.25 mV, or (25 x 10-6) (VREF), over the temperature range of operation. The AD711 is a suitable op amp. The op amp has a wide bandwidth and high slew rate and is recommended for ac and other applications requiring fast settling. General Ground Management: Since the AD7538 is specified for high accuracy, it is important to use a proper grounding technique. AC or transient voltages between AGND and DGND can cause noise injection into the analog output. The simplest method of ensuring that voltages at AGND and DGND are equal is to tie AGND and DGND together at the AD7538. In more complex systems where the AGND and DGND intertie is on the backplane, it is recommended that two diodes be connected in inverse parallel between the AD7538 AGND and DGND pins (1N914 or equivalent).
Figure 9. AD7538-8086 Interface: Multiple DAC System
REV. A
-7-
AD7538
AD7538-MC68000 INTERFACE
Figure 10 shows the MC68000 processor interface to a single device. In this setup the double buffering feature of the DAC is not used and the appropriate data is written into the DAC in one MOVE instruction.
Figure 10. AD7538-MC68000 Interface
DIGITAL FEEDTHROUGH
The digital inputs to the AD7538 are directly connected to the
Figure 11. AD7538 Interface Circuit Using Latches to Minimize Digital Feedthrough
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Pin Plastic Suffix (N)
24-Pin Cerdip (Suffix Q)
-8-
REV. A
PRINTED IN U.S.A.
C1054-9-5/87
microprocessor bus in the preceding interface configurations. These inputs will be constantly changing even when the device is not selected. The high frequency logic activity on the bus can feed through the DAC package capacitance to show up as noise on the analog output. To minimize this Digital Feedthrough isolate the DAC from the noise source. Figure 11 shows an interface circuit which uses this technique. All data inputs are latched from the bus by the CS signal. One may also use other means, such as peripheral interface devices, to reduce the Digital Feedthrough.

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